In a conventional NAND flash memory, a verification operation is carried out when data is written. This technique is disclosed in Japanese Patent No. 3935139, for example. In this case, the following function (hereinafter, referred to as a pseudo-pass function) has been known. According to the function, if a bit error is less than a predetermined number in the verification result, the bit error is allowed and a program sequence is completed. The foregoing function is used, and thereby, a data write speed is improved.
In order to use the function, a circuit technique of counting the number of bit errors is required. Conventionally, this circuit technique is realized by employing a binary search to specify a failed column (column including the bit error).
However, when the foregoing binary search is employed, time is taken to specify a failed column, and a NAND flash memory must be configured to have a mass capacity; as a result, a data write speed is lowered.
Moreover, according to the column specification using the binary search, a column address is activated by the half from a state of being all selected, and further, the remaining half is activated, . . . to specify a failed column. Then, a failed column must be searched every activation. For this reason, a column address circuit is occupied for a period of specifying a failed column. As a result, it is impossible to accept an address input externally for the foregoing period. In order to accept the address input, the following operation is required. Namely, a failed column search is interrupted, and after address input, the failed column search must be retried from the beginning.